1. Field of the Invention
The present invention relates to a multi-layer printed circuit board, and more particularly, to a multi-layer printed circuit board having a plurality of bump connection pads for mounting a Ball Grid Array Packaging type semiconductor component, and its fabrication method. The present invention also relates to a printed circuit board having a thin printed circuit board compared to that of conventional art and which is capable of solving a problem of defective attachment of a bump due to a void in a blind via hole (referred to as ‘BVH’, hereinafter).
2. Description of the Background Art
FIG. 1 is a sectional view of a multi-layer printed circuit board in accordance with the conventional art.
As shown in the drawing, a plurality of resin layers 3a and 3b are stacked by a built-up method, and circuit patterns 5a, 5b and 5c made of metal thin layer are formed on each resin layer 3a and 3b. 
A blind via hole 7b is formed penetrating the resin layer to connect the upper circuit pattern 5c and the lower circuit pattern 5a. The blind via hole 7b is formed having a reversed conical shape wherein the diameter of the entrance is greater than that of the bottom. The entrance of the upper via hole 7b and a lower via hole 7a is positioned in the same direction (the upward direction in FIG. 1).
Plated layers 9a and 9b are formed at the inner side of the blind via holes 7a and 7b, respectively. The plated layer 9a, 9b are also extendedly formed on the upper surface of the upper circuit pattern 5c and the lower circuit pattern 5a. Thus, the upper circuit pattern 5c and the lower circuit pattern 5a are electrically connected by the plated layers 9a, 9b. 
An inner lead bump 11 for electrical connection with a semiconductor chip component (now shown) is attached at the upper portion of the plated layer 9b on the upper surface of the blind via hole 7b. 
A solder resist layer 12 covers the upper surface of the plated layer 9b and the resin layer 3b except for the portions where the inner lead bump 11 is attached. That is, in the conventional multi-layer printed circuit board of FIG. 1, the inner lead bump 11 is attached in the blind via hole.
A method for fabricating the above described printed circuit board will now be explained.
First, a copper clad laminate (CCL) is prepared wherein an upper metal thin plate 4a and a lower metal thin plate 4b are coated on both surfaces of the lower resin layer 3a. 
The upper metal thin plate 4a and the lower resin layer 3a are etched to form a lower blind via hole 7a. The lower plated layer 9a is formed at the side wall face and the bottom surface of the lower blind via hole 7a to electrically connect the upper and the lower metal thin plates 4a, 4b. 
Thereafter, the upper metal thin plate 4a and the lower plated layer 9a are patterned to form the lower circuit pattern 5a. 
Next, the resin layer 3b and a metal film 4c are formed at the upper surface of the lower plated layer 9a and the lower resin layer 3a. 
And then, the metal film 4c and the upper resin layer 3b are partially etched to form the upper blind via hole 7b. At this time, the upper surface of the lower circuit pattern 5a is exposed through the upper blind via hole 7b. 
And, the upper plated layer 9b is formed at the upper surface of the metal film 4c, at the inner wall face of the upper blind via hole 7b and at the upper surface of the lower plated layer 9a exposed at the bottom of the upper blind via hole 7b. 
Then, the upper plated layer 9b and the metal film 4c are patterned. The patterned metal film 4c becomes the upper circuit pattern 5c. The upper circuit pattern 5c and the lower plated layer 9a are electrically connected by the upper plated layer 9b. 
Next, the solder resist layer 12 is formed at the upper surface of the upper plated layer 9b and at the exposed upper resin layer 3b except for the inside of the upper blind via hole 7b. The upper surface of the upper plated layer 9b, which is exposed by not being covered with the solder resist layer 12, is a pad for attaching a bump for mounting a chip component.
And then, the solder bump 11 is attached at the upper surface of the upper plated layer 9b within the upper blind via hole 7b, that is, at the pad.
However, the printed circuit board fabricated according to the conventional method has the following problems.
For example, first, since the bump 11 is formed at the upper portion of the upper blind via hole 7b, the air in the upper blind via hole 7b is not discharged externally, forming an air void 14, or the air flows into the bump 11 and remains there. Then, due to the heat generated in mounting a chip component on the printed circuit board or from the intense heat generated from use of its product, the blind via hole or the air void of the bump swells to generate a crack to the printed circuit board around the bump or to deteriorate the attachment state of the chip components, resulting in damage to the packaging state of the chip components of the printed circuit board.
Secondly, in an effort to solve the problem, a Japanese Patent Laid Open No. 10-284846 discloses a method in which, for mounting the bump, the pad is extendedly designed in the vicinity of the blind via hole, avoiding the blind via hole. In this case, however, a problem arise in that the printed circuit board increases in size.
Thirdly, in a flip chip fabricating process, when an under filler is filled between the chip and the printed circuit board to correct a difference in the heat expansion between the chip mounted on the printed circuit board and the printed circuit board, the under filler is not completely filled in the blind via holes 7, causing a problem in that the printed circuit board is deformed due to thermal impact.
Lastly, in the case of forming a flexible printed circuit board, if the resin layer is too thin, it is inconvenient to handle it during the fabricating process, degrading yield rate. A solution to this problem is to forming the resin thick, but it is difficult to decrease the thickness of the printed circuit board.